Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a line of a semiconductor device that improves resistance to electromigration (EM) degrading due to an increase of packing density.
Background of the Invention
Recently, with the increase of packing density of a semiconductor device, a width of a line and the size of a contact hole have been decreased. For this reason, density of current applied to the line also has been increased. Accordingly, problems related to reliability of the line due to EM are becoming a major concern for the semiconductor device.
EM generally is defined as atoms constituting a line that move when current flows into the line due to electrons. Characteristics of the EM depend on at least the following factors: the types of line (i.e. material, crystalline structure, and fine structure); line width; line thickness; a contact structure; a driving current density; and an operational temperature.
Generally, to improve the EM characteristics of the line, the fine structure and the crystallization structure of the line are controlled. Additionally, an Al alloy and a layered structure are used.
Initially, the relation between the EM, the fine structure and the crystalline structure is as follows. Al has a polysilicon structure after deposition. In this case, the relationship between the EM, the fine structure and crystalline structure is expressed as Equation (1) below.                     MTTFα        ⁢                  S                      σ            2                          ⁢                              ln            ⁡                          (                                                I                                      (                    111                    )                                                                    I                                      (                    200                    )                                                              )                                3                                    Equation        ⁢                  xe2x80x83                ⁢                  (          1          )                    
Here, MTTF denotes a median time to failure, S denotes a size of a grain, "sgr" denotes a distribution of the crystalline grain, and       I          (      111      )            I          (      200      )      
denotes (111) alignment of the line. Accordingly, the EM characteristics can be improved by greatly and uniformly maintaining the size of the grain and controlling the crystalline structure to have a (111) alignment.
The relationship between the EM and the Al alloy is as follows. If a line is formed of Alxe2x80x94Cu compound (Al3Cu) in which an element such as a Cu atom is added to Al, Al atom mobility is reduced due to a grain boundary of the Alxe2x80x94Cu compound and the Cu atom is entered into the grain boundary to occupy a vacant site. Because of this, the Al atom mobility is deteriorated, thereby improving the EM characteristics.
Finally, the relationship between the EM and the layered structure is as follows. A factory metal film, such as Ti, TiN, TiW, and W, is deposited before and after deposition of the line. Thus, it is possible to prevent a short from occurring, even if a void is formed within the line. Also, since an anti-reflective coating (ARC) film prevents xe2x80x9cHillockxe2x80x9d from occurring, characteristics can be improved.
A related art method for forming a line of a semiconductor device will now be described with reference to the accompanying drawings.
FIGS. 1A-1D are sectional views of a conventional process for forming a line of a semiconductor device. FIG. 2 shows a conventional internal structure of a line of a semiconductor device.
As shown in FIG. 1A, a lower line 12 is formed on a first insulating film 11, and an oxide film 13 is deposited on the lower line 12. A plug (not shown) is then formed in the oxide film 13 to electrically connect the lower line 12 with an upper line metal film 15, which will be formed later.
To improve the adhesive property between the oxide film 13 and an upper line metal film 15, which will be formed later, an adhesive layer 14 is formed on the oxide film 13. Typically, Ti or TiN is used as the adhesive layer 14. The upper line metal film 15 is formed on the adhesive layer 14. At this time, the upper line metal film 15 is formed by depositing an Al film.
As shown in FIG. 1B, an ARC film 16 is formed to prevent anti-reflection from occurring during an exposure process. A photoresist 17 is then deposited on the entire surface of the ARC film 16. Here, TiN is used as the ARC film 16.
As shown in FIG. 1C, the photoresist 17 is selectively patterned by exposure and developing processes.
As shown in FIG. 1D, the ARC film 16, the upper line metal film 15, and the adhesive layer 14 are selectively removed using the patterned photoresist 17 as a mask to expose a portion of the oxide film 13. At this time, the upper line 15a is formed by selectively removing the upper line metal film 15. Subsequently, an annealing process is performed, and a second insulating film 18 is deposited. Thus, a line of the conventional semiconductor device is completed.
In the line of the semiconductor device formed as above, since the upper line 15a is long, as shown in FIG. 2, a number of vacancies 19 occur. Additionally, the vacancies 19 move due to electron movement and current flow from the lower line 12 to the upper line 15a through a plug 21. Accordingly, the vacancies 19 are coupled to a void 20, thereby increasing the size of the void 20.
The aforementioned conventional method for forming a line of a semiconductor device has several draw-backs.
First, if the width of the line is thick, the Al line has a polysilicon structure. In this case, line short due to the void is caused as a result of the occurrence of a number of grain boundaries in which electrons can move.
Second, since the line is long, a number of vacancies occur. The void is enlarged as the vacancies are coupled to the void, thereby causing line short due to the void.
Finally, due to an increased stress of the line as a result of vacancies occurring in the line, the resistance to EM is reduced.
Accordingly, the present invention is directed to a method for forming a line of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of conventional methods.
An object of the present invention is to provide a method for forming a line of a semiconductor device in which a barrier film is formed within the line to reduce a width and length of the line, thereby improving resistance to EM.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for forming a line of a semiconductor device according to the present invention includes: forming a first insulating film on a semiconductor substrate in which a lower line is formed; depositing an adhesive layer on the first insulating film; forming an upper line metal film on the adhesive layer to be connected with the lower line through a plug that passes through the first insulating film; depositing an ARC film on the upper line metal film; forming a barrier film on the upper line metal film by barrier ion implantation using a mask which exposes a predetermined region of the ARC film; selectively removing the ARC film, the upper line metal film, and the adhesive layer by photolithography and etching processes to form a plurality of trenches, so that an upper line is formed with the upper line metal film; and forming a second insulating film on an entire surface including the trenches.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.